Delay flip-flop circuit



Feb. 16, 1965 R. N. MELLoT'r 3,170,075

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Feb. 16, 1965 R. N. MELLOTT DELAY FLIP-FLOP CIRCUIT Filed July 24, 19622 Sheets-Sheet 2 Ii?. J

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UnitedStates Patent AC),

. 3,170,075 DELAY FLIP-FLD? CHRCUET Robert N. Meiiott, Northridge,Calif., assigner, by mesne assignments, to The Bunker-Ramo Corporation,Starniord, Conn., a corporation or' Delaware Filed .Fuly 24, 1962, Ser.No. 212,023 4 Claims. (Cl. SWL-83.5)

This invention relates to bistable-state circuits of the type which aredesignated as flip-flop circuits and, more particularly, to improvementstherein.

The` circuit to which the appellation flip-hop circuit is appliedusually is an arrangement of at lent two tubes or transistors with `anetwork cross-connecting these,` so that, in response to an inputsignal, `one of the tubes or transistors can be driven into conductionand the other cut ofi, and then, in response to another input signal, a

Alternatively, the two transistors or tubes may be biased so that theyare driven fromlight conduction to heavyrconduction alternatively inresponse to input signals. -The' speed `with which these Hip-flopinterchange conduction states is usually 'determined by the timeconstants of the cross-coupling network, which serves as a limitationupon the speed of operation. vrFurthermore, if it is desired to operatethe flip-flop in response to a clock as well as a driving signal, it isnecessary to. provide a logic Vcircuit to `take care of this situation.v l

The ilip-ilop circuit normally has two stable states -and may be drivenfrom one to the other by the input signals; An output is taken from oneof the .two stages to indicate the state of stability of thepflip-opcircuit. 2 t

An objectfof this invention isto provide a bistable-stat circuit whichdoes notV have a crossscoupling network.

Another. object oi this invention is to. provide a bistablestate circuitwhich will operate in response to va triggering and clocksigr121l,without` requiring any 'external logic.-

Still another object'of the presentvinvention is thel progvisionof anovel and"useful'bistablefstatejcircuit.

CCv

p FIGURE 2 is a circuit diagram of another embodiment or" the invention;i f

FIGURE 3 is a block circuit diagram showing the embodiment of theinvention being used as a shift-register stage; and i FIGURE 4 is acircuit diagram of a modiication of FIGURE 3, showing how it may beemployed with hold and clear signals being applied. J

The circuit in taccondance With this invention isa bistable-statecircuit which has a single input and a single output. The output has thesame information pattern as the input,rbut occurs after a one-bit timedelay. Thus, it provides an output representative of the input, oneclock pulse later. w

Reference is now made to FIGURE 1, wherein there may be seen a circuitdiagram of an embodiment of this invention. This includes an input NPNtype transistor 19, which is employed to alter the state of conductionof an NPN type transistor 12 and a PNP type transistor 14. Aninput-signal source 16 applies signals via anyk suitable logical gatingcircuit 17 to the base of transistor 10. The base of transistor 1? isbiased Vby being conneoted through a resistor 18 to a terminal 2h, towhich av source of operating potential, designated as +135 volts isapplied. The base of transistor 10 isalso connected throughva diode 22to Ianother terminal 2d, to which a biasrpotential source of -4 volts isapplied.

The emitter of transistor 10 is connected to a junction 26, to whicholoci; Y Y plied through a diode 30. Also, a resistor 32 is connectedfrom a terminal 34 tothe junction ,26. A negative operating-potentialsource on theA orderv of '-1'3.5, volts is applied to the terminal 34.'The collector of transistor lil is connected to the terminal .20 througha load-resistor 36. The collector of transistor' 1) isfalso.

directly connectedto the base ofthe PNP transistor 14 and -tothe emitterofthe transistor14 vthrough a`j"diode -YetI another object, ofthepresent invention is fthe-pros 740 f vision of a useful bistable-statecircuite.whichL can `be employed as a delay ipflop or as abasicshiftjre'gister stage. i Y

@These and other objects lof Ithe invention may beiY i achieved inlanlarrangement wherein the bistable-state circuit comprises'at leasttlu'eetransistors. These three transistors are interconnected sothat inAresponse to one type of,input signal, designated asV a falseinputfsignal,

anda clock pulse, thevrst transistor orf-the.-threedrives the thindtransistor into conduction, which, in turn, drives `the'secondtransistor into conduction. Thetsecond and third transistors thereaftermaintain themselves in conduction.

Upon therapplication `olfa second type of signaL'designated Iasa"true,signal, anda 'clock pulse to the rst tranf sistor, thersttransistor isf held biased off and further conduction inthe secondtransistor is terminated, xvherre-A upon Vthe third transistor is alsobiased Oli.` If the second fand fthird transistors were already intheir. cutoltAc'ondi-'f' tion whentlie true signal is. applied,they-will remain in that condition.v Y

581. The emitter` of transistor 14 is `connected .via a ter-Aminaliffogmund. -f f The collector of NPN transistor 12-i`s1connectedthrough a resistor 41? in series with the resistor'o; "The l Y collectorof transistor,12Visalso-connectedfto the'collec- 1 tor-of transistor4i'rthrough a diode 42. .'Thefcfcrarllectorl of rtnansistor 14isconnected to the baseof'tra'nsistor 12 from terminal 34I to thecollector of'tr-'ansistor 14;

The norv'el'` features that areconsidered characteristic of thisinvention are set forth withA particularityv in the appendedA claims.The invention itself, both .as toits organization and method ofoperation, as well as` additional objects and advantagesthereof, willbest be' under-` stood from the following description when read inconnection with the accompanying drawings, in which:V

FIGURE lis a circuit diagram of an embodiment of the invention; Y

f :A capacitor 48 is connected. in parallelwithzthe resistor 44. vAdiode Silis connected between "the'juncti'on 26 and the base-oftransistor 12. Thejb'ase Vorf-transistor .12 1s *connected-'through' a1diode'152 ,to"a`ter1ninal 54 to which a source of bias potential, lonthe order-,oft ,-*4 volts, is connected. The emitter otransistor 12isVconnected to va dioide'o tothe terminalys. The emitter of transistor 12is also connectedthrough'a resistordo' thenegative operatingpotentialterminall34. The coli lector-of transistor 14 isV connected to an outputterminal 60, from which Voutput from the circui'tis derived;

As stated previously, the crcuihrshownzin FIGURE. 1"

hast two4 stable. states. Considenpiirst, lconditionsfvvhich arisewhenthe transistor` 14- isconducting` AripoutputV signal. isderived fromtheoutputqterminal 60, since current ows through the transistorandlthroughresistor fie. Current also flows through resistor 44 to thebase Junction of transistor 112. At this point, current branches tosupply base drive. to transistor 12 and ,a current flows through fthediode 52 to the -4 Vvolt bias sourcetconnected to the terminal 54. Diode52 Y is asilicondiode, preferably, and, since the forward on the'orderof 0.5 to0.7 volt, the base potential of transistor 12 isestablished'between 'Lp-3.5 tof-3.3 volts;

` emitter potential will be a few tenths of a volt more negapulses froma source 28.1nay be ap drop -thereacross is,

TheA

tive than the base potential. However, it will be more positive than a4.0 volts. This means that diode 56 is cut off and that the currentthrough the resistor 58 flows from the emitter of transistor 12. Thevalue of resistor 58 is selected such that the collector currentdemanded by transistor 12 cannot be supplied through the resistor 36without pulling the base of transistor 14 negative. Thus, the feedbackloop is completed, and both transistors 12 and 14 are maintained in theconducting state. Resistor 40 and diode 42 limit the conductingcondition of transistor 14.

Consider, now, the situation where transistor 14 is cut off. Thecollector of transistor 14 is at substantially 13.5 volts, and,accordingly, the base of transistor 12 is also at this potential, inview of the connection thereto of resistor 44. The emitter of transistor12 is established at approximately 4.3 volts, due to the current lowingfrom the 4 volt source through terminal 54 through diode 56 and thenthrough resistor S8 to the terminal 34. Transistor 12 is thusreverse-biased by the difference in the base and emitter voltages and ismaintained nonconducting. With no collector current owing in transistor12, current ows from the terminal through resistor 36 through diode 38to ground, which results in a backbias being applied between base andemitter of transistor 14 by the forward drop across diode 33. This keepstransistor 14 cut off.

In the interval between clock pulses, the emitter of transistor 10 ismaintained at the clock-pulse reference potential, which is atapproximately ground potential, by current flowing from the clock-pulsesource 2S through diode through resistor 32 to terminal 34. Currentthrough resistor 18 and diode 22 to terminal 24 prevents the base oftransistor 1i) from being more than 0.3 to 0.5

volt above 4 vo1ts,'so` that transistor 10 is cut oil. Also,

cut olf between clock pulses. Thus, with both transistor 10 and diode 50nonconducting, the input circuit is essentially disconnected from, andcannotvaffect the status of, transistors 12 and 14.

Consider, now, the operation of lthe-circuit at clockpulse time. Assume,first, a false signal is applied from the input-signal source 16 to theVlogical gating circuitry 17 the output of which is connected to thebase of transistor 10. A false signal essentially does not alter thepotentials at .the base of transistor 10 from the status just described.At clock-pulse time, a negative pulse of approximately six-volts peak isapplied from the clockpulse source 28 to the diode 30. As a result,diode 30 is no longer conductive, and the emitter of transistor 10canswing negative from the potential applied at terminal 34. As aresult, transistor 10 is rendered conductive, which applies base drive`to transistor 14 for causing it tov become conductive, if it was notalready conductive. Transistor 14, in turn, through resistor 44 andcapacitor 48 applies base drive to transistor 12, to render itconductive. Accordingly, the flip-flop circuit is triggered into itsfalse state. If transistor 14 was already conducting at the time whentransistor 10 is rendered conductive, then the base drive fromtransistor 10 only makes transistor 14 conduct the harder, and does notturn it oi.

The application of a true signal from the input-signal source 16,through the logical gating circuitry to the base of transistor 10 is setat approximately 7 volts. At clock-pulse time, the emitter of transistor10 is permitted to swing negative until diode 50 conducts, if transistor12 is already conducting, or to 6 volts, if transistor 12 is cut off.Accordingly, transistor 10 remains reversebiased. If transistor 12 wereconducting, current through diode 50 and resistor 32 results in theapplication of ay potential to the base of transistor 12, which causesit to become cut oil?. This, in turn, results in the application of acut-off potential to the base of transistor 14. Thus, both transistors12 and 14 go to their true conditions. If the transistors 12 and 14 werenonconducting at the time the true input was applied to the base oftransistor 10, they would remain in their nonconducting state.

By way of illustration of an operative embodiment of the invention, thetypes of transistors and the values of the potential sources areprovided. This is illustrative only and the invention should not beconsidered as limited thereto.

Reference is now made to FIGURE 2, which is a less expensive version ofthe embodiment of the invention shown in FIGURE l. Structures whichfunction similarly to those shown in FIGURE 1 bear the same referencenumerals. The following changes are made in FIGURE l to obtain FIGURE 2.Diodes 30 and 42 are omitted, the resistor 40 is omitted, and a directconnection is made from the collector of transistor 12 to resistor 36.In place of diodes 22, 38, and 52, the respective resistors 62, 64, and66 are inserted, which have their resistance values selected to providethe same type of voltage drop thereacross as occurs when current tlowsthrough these diodes. Finally, the resistor 32 is disconnected from theterminal 34 and instead is connected directly to the clock-pulse source28.

The circuit shown in FIGURE 2 operates in substantially the same manneras the circuit shown in FIGURE l. Upon the application of a false-inputsignal to the base of transistor 10, nothing happens until the nextclock pulse. At this time, the emitter of transistor 10 is pullednegative with respect to its base, whereupon it is rendered conductive.This applies a drive to the base of transistor 14, to cause it to goconducting, if not already in the conducting state. When transistor 14is rendered conductive, a signal is applied from its collector to thebase of transistor 12, to drive transistor 12 into conduction. Upon theapplication of a true-input signal to the base of transistor 10, thesucceeding clock pulse, while pulling the emitter down to substantially6 volts, is not suihciently negative to drive the transistor 10 intoconduction. If

. transistor 12 is conducting, then the clock pulse causes Y diodel 50to become conductive, whereupon the potential applied to thebase oftransistor 12 is more negative than that existing at its emitter, andthe transistor is cut olf. When transistor 12 driven to cutot, a cutoffpotential is applied to the base of transistor 14, and it, too, isdriven to cutoff. If transistor 12 were nonconducting at the time theclock pulse occurs, then a voltage of 13.5 Volts exists at its base, anddiode 50 remains non-conducting. Thus, transistor 12 and alsotransistor14 remain nonconducting at this time.

FIGURE 3 is a combined circuit and block diagram which shows how thecircuit shown in either FIGURE 1 or FIGURE 2 may be used as ashift-register'stage. The

rectangle 70, which is called circuit for transistors 12 and 14,represents the circuitry shown in either FIGURE l or FIGURE 2, to whichtransistor 10 is connected. All that is necessary to make a shiftregister of a plurality of bits is to connect the output terminal 60.0fone bit to the input terminal, here shown as 72, of the following bit ofthe shift register. The coupling network required between bits comprisesa series resistor 74, connected between the input terminal 72 and thebase of transistor 10 and a capacitor 76, which is connected between thebase of the transistor and ground. The resistor 74 and capacitor 76serve as a simple delay network between stages. If the transistors 10and 12 of a preceding stage are conducting, then, upon the occurrence ofa clock pulse, the succeeding-stage transistors 10 and 12 will beconverted to a conducting condition, if not already so. If thetransistors in the preceding stage are not conducting, then, upon theoccurrence of a clock pulse, the transistors 10 and 12 of the succeedingstage are rendered `nonconductive if not already so. The mechanics Vofthe.

circuit operations, in response tothe inputs and clock pulses, areidentical with what has been described in connection with FIGURES 1 and2.

FIGURE 4 shows a circuit diagram of a shift-register stage in accordancewith this invention which has hold and clear control features addedthereto. FIGURE 4 is essentially the identical arrangement as FIGURE 3,

-except that hold signals are applied from a hold-signal Y source 80 tothe emitter of transistor llt) Vthrough a diode 82. Further, resistor 66is connected to a clear-signal source 84, instead of to the h4 Volt biassource. The

circuit components, which perform identically with those componentsshown in FIGURE 2, have the Same reference numerals applied thereto'.Inf operation, the circuit and said third transistor `collector,"me`ans.connecting said first transistor collector to said junction, athird;resistor connected between said first terminal and said firsttransistor base, avfourth resistor connected between, said thirdtransistor collector and said third terminal, a fifth resistor connectedbetween said second transistor emitter and said third terminal, a thirddiode, a source of negative potential, means connecting said third diodebetween said source o'f negative potential and the base of said secondtransistor, a fourth diode, means connecting said fourth diode betweensaid lnegative potential source Vand the will have a false state Withtransistors l2 and 14 conducting and ajtrue state with transistors 12and 14 .noncon ducting.A If a signal applied from the hold-signal sourceis more negative thanthe negative peak of the clockpulse signalreceivedfrom the clock-pulse signal source 28,l andif the signal applied fromthe clear-signal source 84 is at -4 voltsther 1 the circuit will operateas a delay 1 element in a` shift register. That is, itsoutput will betrue orvfalse in accordance with the signal appliedto the inputterminali'l uponrrthe application of the next clock pulse.

If the clear signalreceived from the clear-signal source S11-remains at-4 volts, but the hold signal received from the hold-signal source ischanged to ground potential,`

clock pulses are prevented from affecting the basic flipfiop circuit.Thus,the state of the flip-iiop circuit remains the same asit'was justprior to the application of the hold signal. The reason this isl so isthat the input signals applied to terminal 72 Awill Vserve either toapply 13.5 volts o r a few volts below ground potential to the base oftransistor l0. Ineither case, the emitter of transistor 10 is heldclamped to substantially ground potential, and therefore the transistorwill not be affected by any input signal. The cathode'of diodeSil isclamped at substantially ground potentiahand therefore clock pulsescannot get through to drive transistor 127into conduc- The transistors12 and 14 can be forced to their false .or conducting state byapplyingla signal from the clearsignal source 84, which is sufficiently positivetoV cause transistor i2 to become conductive.

which is the voltage to which the emitter is clamped through diode 56when .transistor 12 is nonconductive.,y vBy making the clear signal fromthe clear-signal source 84 negative with respect to .4 volts, the basicnip-flop stage, consisting of transistors l2 and 14, can be forced tothe true state, with these transistors being cut off.

.This occurs since, as previously explained, when a suf` ficientlynegative signal is vapplied to the base of transistor l2, it is cut offand applies a cutoff signal'through its collector tothe base oftransistor 14.

vThere hasbeen accordingly described and shown hererin Ya novel, useful,bistable-state circuit wherein no crossover networkvis required `andwherein the output has the same informationpattern as the input but witha one-bit time delay.

I claim:

' l. A bistable-state circuit comprising first, second, and

third` transistors, said first and second transistor being of a typewhich is complementary to the third transistor type, all saidtransistorshaving base, emitter, and collector electrodes, first, second, and thirdterminals, means connecting said third transistor emitter to said secondterminal, a first and second resistor connected in series and having ajunction therebetween, means connecting said' first and second resistorsbetween said first terminal and said second transistor vcollector, adiode connected between said junction and said second terminal, a seconddiode connected between said second transistor collector This means avol- Y tage level which` is slightly more positive than .-4 volts,

"emitter of said secondtransistor, -a fifth diode, 'means conj nectingsaid fifth diode between the base of saids'econd transistor and theemitter of said rst transistor, a Vsixth resistor connected between saidfirst transistor emitter and said third terminal, a sixth diodeconnected between said first transistor base and said 'source ofnegative potential, a clock-pulse input terminal, a seventhfdiodeconnected between saidy clock-pulse input terminal and said firsttransistor emitter, an eighth resistor connected between said thirdtransistor base and said second transistor collector, means forapplyinga positive operating potential between said first and second terminals,means` for applying a negative operating p'tential between said thirdand second terminals, means for applying input signals and clock pulsesto said first transistor base and to said clock-pulse terminalrespectively, tov determine the state' of conduction of' said first,second, and third transistors, and means for deriving an output fromsaidthird transistor collector indicative of thestate of conductiontofsaid third transistor. Y Y 2. A bistable-state circuit comprising first,second, and third transistors, said first and second transistors beingof a type which is complementary to the third transistor type, all saidtransistors having base, emitter, and collector Y electrodes, first,second, and third operating-potentialterrninals, a first resistorconnected'between said first terminal'and the collector ofsaidsecond-transistor, a second resistor connected between said secondtransistor collector and the emitter of said third transistor, meansconnecting said third transistor emitter/to said second terminal, meansconnecting said third transistor base to said secondtransistorgcollector, means connecting said first transistorcollectorfto saidnsecond transistor collector,V

a third resistor connected between said second transistor base and saidthird transistorcollector, a capacitor connected in parallel .with saidthird resistor, ay first diode connectedbetween said first transistoremitter and said second transistor base, a-source` of negativepotential, a fourth resistor connected between said sourceof negativepotential and said second vtransistor base, a second diode connectedbetween saidsource of negative potential and said second transistoremitter, a fifth resistor connected between said third transistorcollectorandY said third terminal, a sixth resistor connected betweenvsaid second transistor emitter and said third terminal, a sixthresistor connected between said first terminal and said first transistorbase, a sixth resistor connected between said first transistor base andsaid source of negative potential, a clock-pulse input terminal, a4ninth resistor connected between said clock-pulse inputterminal andtheemitter of said first transistor, means for applying input signals tosaid first transistor'base, means for applying are provided coupling thecollector of said first transistor to the base of said second transistorfor rendering said second transistor nonconductive when said firsttransistor is nonconductive and wherein second means are providedcoupling the collector of said second transistor to the base of saidiirst transistor for rendering said rst transistor conductive when saidsecondtransistor is conductive and wherein third means are providedrespectively, coupling said first and second transistor emitters tosources of reference potential, an input circuit for respectivelycontrolling said first and second transistors, said input circuitcomprising:

input signal'source means capable of selectively providing first andsecond output signals; clock pulse source means for periodicallyproviding clock pulses; a third transistor having an emitter, acollector, and

a base; means applying said input signalrsource means output signal tosaid third transistor base and said ciocl; pulses to said thirdtransistor emitter; said third transistor being rendered conductive inresponse to said first output signal and one of said clocl; pulses;means connecting said third transistor emitter to said first transistorbase for rendering said first transistor nonconductive in response toone of said clock second transistor nonconductive when said firsttransistor is nonconductive and wherein second means are providedcoupling the collector of said second transistor to the base of saidiirst transistor for rendering said first transistor conductive whensaid second transistor is conductive and wherein third means areprovided respectively coupling said first and second transistor emittersto sources of reference potential, an input circuit for respectivelycontrolling said iirst and second transistors, said input circuitcomprising:

input signal source means capable of providing first and second outputsignals; clock pulse source means for periodically providing clockpulses; a third transistor having an emitter, a collector, and

a base; means applying said clock pulses to said first transistor basefor normally rendering said first transistor nonconductive; meansapplying said input signal source means output signal and said clockpulses to Said third transistor base andV emitter respectively forrendering said third transistor conductive inrresponse to said firstoutput signal and one of said clock pulses; and means responsive to saidthird transistor conducting for rendering said secondV transistorconductive to thus inhibit said clock pulse from rendering said firsttransistor nonconductivc.

References Cited by the Examiner UNITED lSTATES PATENTS 2,994,002 7/61Cooke-Yarborough 307-885 3,002,109 9/61 Baird 307-885 3,008,056 llt/6lWanlass 307-88.5

JOHN W. HUCKERT, Primary Examiner. ARTHUR GAUss, Examiner.

3. IN COMBINATION WITH A FLIP-FLOP CIRCUIT INCLUDING FIRST AND SECONDCOMPLEMENTARY TYPE TRANSISTORS, EACH HAVING AN EMITTER, A COLLECTOR, ANDBASE WHEREIN FIRST MEANS ARE PROVIDED COUPLING THE COLLECTOR OF SAIDFIRST TRANSISTOR TO THE BASE OF SAID SECOND TRANSISTOR FOR RENDERINGSAID SECOND TRANSISTOR NONCONDUCTIVE WHEN SAID FIRST TRANSISTOR ISNONCONDUCTIVE AND WHEREIN SECOND MEANS ARE PROVIDED COUPLING THECOLLECTOR OF SAID SECOND TRANSISTOR TO THE BASE OF SAID FIRST TRANSISTORFOR RENDERING SAID FIRST TRANSISTOR CONDUCTIVE WHEN SAID SECONDTRANSISTOR IS CONDUCTIVE AND WHEREIN THIRD MEANS ARE PROVIDEDRESPECTIVELY, COUPLING SAID FIRST AND SECOND TRANSISTOR EMITTERS TOSOURCES OF REFERENCE POTENTIAL, AN INPUT CIRCUIT FOR RESPECTIVELYCONTROLLING SAID FIRST AND SECOND TRANSISTORS, SAID INPUT CIRCUITCOMPRISING: INPUT SIGNAL SOURCE MEANS CAPABLE OF SELECTIVELY PROVIDINGFIRST AND SECOND OUTPUT SIGNALS; CLOCK PULSE SOURCE MEANS FORPERIOCICALLY PROVIDING CLOCK PULSES;